Field of the Invention
The present invention relates to an arithmetic apparatus based on digital signal processing.
Description of the Related Art
An arithmetic algorithm called “CORDIC (COordinate Rotation DIgital Computer)” which implements coordinate rotation of complex number data on a complex plane and coordinate rotation of two-dimensional coordinate data on a two-dimensional plane by only bit shift and addition and/or subtraction is disclosed in “J. E. Volder, “The CORDIC trigonometric computing technique”, IRE Transactions on Electronic Computers, EC-8:330-334, 1959”. Also, multidimensional signals are recently advancing as signal processing advances, and it has become necessary to perform a process of obtaining, for example, an optimal solution by solving multidimensional simultaneous equations in real time. Therefore, demands have arisen for an arithmetic apparatus having a high operation accuracy and high processing performance.
For example, when using the above-described CORDIC, several tens of pipelined CORDICs having 20 or more stages are sometimes necessary for an arithmetic operation of 20 or more bits. Since, however, it is necessary to stably operate the system at a high frequency, demands have arisen for a compact CORDIC having a smaller circuit configuration.
Accordingly, techniques capable of efficiently performing a coordinate rotation calculation with a small delay in the CORDIC are disclosed in “Qiang Gao, Louise Crockett and Robert Stewart, “COARSE ANGLE ROTATION MODE CORDIC BASED SINGLE PROCESSING ELEMENT QR-RLS PROCESSOR”, 17th European Signal Processing Conference (EUSIPCO 2009) Glasgow, Scotland, Aug. 4-28, 2009″ and Japanese Patent No. 3283504 (patent literature 1). In addition, an improved technique called a double-rotation CORDIC is disclosed in “N. Takagi, T. Asada, and S. Yajima, “Redundant CORDIC methods with a constant scale factor for sine and cosine computation”, IEEE Trans. Computers, vol. 40, no. 9, pp. 989-995, September 1991”.
When the contents of actual arithmetic operations are taken into consideration, however, the vectoring-mode arithmetic performance of the above-described conventional CORDIC arithmetic apparatus is presumably redundant.
That is, in linear algebraic processing of a matrix, the number of vectoring-mode operations of detecting the argument of two-dimensional coordinate data is much smaller than that of rotation-mode operations of rotating the coordinate data based on the detected argument. On the other hand, in the CORDIC of the arithmetic apparatus disclosed in the above-described related art, the vectoring-mode arithmetic performance of detecting the argument and the rotation-mode arithmetic performance of rotating the coordinate data based on the detected argument are equal. That is, the vectoring-mode arithmetic performance of detecting the argument is redundant, so the arithmetic resources are perhaps not effectively used.